DocumentCode

898480

Title

Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework

Author

Alioto, Massimo ; Palumbo, Gaetano

Volume

6

Issue

4

fYear

2006

Firstpage

42

Lastpage

61

Keywords

CMOS logic circuits; Capacitance; Circuit topology; Inverters; Logic circuits; Logic design; Logic gates; MOS devices; Network topology; Resistors;

fLanguage

English

Journal_Title

Circuits and Systems Magazine, IEEE

Publisher

ieee

ISSN

1531-636X

Type

jour

DOI

10.1109/MCAS.2006.264841

Filename

4042106