Abstract :
A high-density dynamic memory cell using the CMOS technology (JCMOS cell) is described. The cell is based on merging three different devices and occupies an area of a single MOS transistor. The cell consists of an enhancement surface MOSFET, a JFET, and a bipolar transistor. The data is stored on the MOS capacitor, sensed by the JFET, and written into the cell using the bipolar transistor. The cell simple processing, small size, high writing and reading speeds, very small leakage current, large readout signal (almost invariant to scaling), nondestructive reading, and suitability for scaling down to very small dimensions, make the JCMOS cell a very attractive candidate for future VLSI dRAM chips. The cell structure and lumped component equivalent circuit are presented. The cell principle of operation and its selective reading and writing are explained. The operation of the memory read/write circuitry is described and simulation results are presented. The cell performance and design considerations are discussed. A test cell was successfully fabricated to verify the cell operation and performance. Experimental results are presented.
