Highly Compact Interconnect Test Patterns for Crosstalk and Static Faults

Author

Song, Jaehoon ; Han, Juhee ; Yi, Hyunbean ; Jung, Taejin ; Park, Sungju

Author_Institution

Dept. of Comput. Sci. & Eng., Hanyang Univ., Ansan, South Korea

Volume

56

Issue

5

fYear

2009

fDate

5/1/2009 12:00:00 AM

Firstpage

419

Lastpage

423

Abstract

The effect of crosstalk-induced errors becomes more significant in high-performance circuits and systems. In this paper, compact crosstalk test patterns are introduced for a system-on-a-chip and board level interconnects considering physically effective aggressors. By being able to target multiple victim lines, 6n, where n is the number of nets patterns are drastically reduced to a constant number 6D, where D indicates the effective distance among interconnect nets. The test quality for static and crosstalk faults are completely preserved with 6D patterns.

Keywords

crosstalk; integrated circuit interconnections; integrated circuit testing; system-on-chip; board level interconnects; compact crosstalk test patterns; crosstalk faults; crosstalk-induced errors; high-performance circuits; interconnect test patterns; static faults; system-on-a-chip; Circuit faults; Circuit testing; Circuits and systems; Crosstalk; Delay; Integrated circuit interconnections; System testing; System-on-a-chip; Test pattern generators; Timing; Crosstalk faults; interconnect test; static faults; system-on-a-chip (SoC); test pattern;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2009.2022373

Filename

4939466