On the pseudo-subthreshold characteristics of polycrystalline-silicon thin-film transistors with large grain size

Author

Li, To-Sing ; Lin, Pole-Shang

Author_Institution

Electron. Res. & Service Organ., Ind. Technol. Res. Inst., Hsin-chu, Taiwan

Volume

14

Issue

5

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

240

Lastpage

242

Abstract

A two-dimensional nonplanar device simulator for polycrystalline-silicon thin-film transistors (poly-Si TFTs) was developed, in which the influence of trapped charges and carrier scattering within the grain boundary region are incorporated into Poisson´s equations and drift-diffusion current formulations, respectively. With this simulator, the I-V characteristics of poly-Si TFT devices can be characterized. TFTs in polycrystalline silicon were fabricated to test the simulator. Special attention was paid to the conduction mechanism in poly-Si TFTs with large grain size. A concept called the pseudo-subthreshold region is presented to explain the observed behavior. The key factors affecting the pseudosubthreshold slope were investigated and elucidated using the simulator.<>

Keywords

elemental semiconductors; grain boundaries; grain size; semiconductor device models; silicon; thin film transistors; I-V characteristics; Poisson equations; Si-SiO/sub 2/; carrier scattering; conduction mechanism; drift-diffusion current formulations; grain boundary region; large grain size; model; polysilicon TFT; pseudo-subthreshold characteristics; trapped charges; two-dimensional nonplanar device simulator; CMOS technology; Conducting materials; Crystallization; Grain boundaries; Grain size; Leakage current; Poisson equations; Scattering; Testing; Thin film transistors;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.215180

Filename

215180