Min-cut partitioning on underlying tree and graph structures

We consider two generalizations of the min-cut partitioning problem where the nodes of a circuit C are to be mapped to the vertices of an underlying graph G, and the cost function to be minimized is the cost of associating the nets of C with the edges of G. Let P be the number of pins, the the number of nodes of G, and d be the maximum number of cells on a net of C. In the first problem the graph G is a tree T. An iterative improvement heuristic is given (Vijayan, 1991) with O(P.t³) time per pass. Our proposed heuristic guarantees identical solutions in O(P.t.min(d,t)) time per pass. The second problem is defined on any graph G. The standard iterative improvement heuristic requires O(P t⁴) time per pass, but our proposed approach guarantees O(P.t.min(d,t)) time per pass. The problems find applications in VLSI physical design and in distributed systems