Optimized silicon-rich oxide (SRO) deposition process for 5 V only flash EEPROM applications

Author

Dori, Leonello ; Acovic, Alexandre ; DiMaria, Donelli J. ; Hsu, Ching-Hsiang

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

14

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

283

Lastpage

285

Abstract

A process for depositing in-situ very-thin (<10 nm) SiO/sub 2/ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO/sub 2/ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm/sup 2/ at J=0.1 A/cm/sup 2/. The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices.<>

Keywords

EPROM; chemical vapour deposition; dielectric thin films; metal-insulator-semiconductor devices; silicon compounds; tunnelling; 10 nm; 5 V; 7 nm; I-V characteristic; LPCVD; Si substrate; SiO/sub 2/-SiO/sub x/; electrical stress endurance; flash EEPROM; high tunneling current; low-pressure chemical vapor deposition; nonvolatile memory devices; polysilicon gate MOS capacitors; single electron injector structure; stacked dielectric; Dielectrics; EPROM; Electrons; Inductors; Low voltage; MOS capacitors; Semiconductor films; Silicon; Stress; Tunneling;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.215199

Filename

215199