A 1-Mbit CMOS DRAM with fast page mode and static column mode

A 1-Mb words/spl times/1-bit CMOS dynamic RAM fabricated with an advanced n-well CMOS technology is described. More than 2.2 million devices are integrated on a 62.5 mm/SUP 2/ silicon chip by utilizing an n-channel memory cell of triple-level poly Si structure and a 1.2-/spl mu/m feature size VLSI process. Novel CMOS circuit design techniques such as the half V/SUB cc/ bitline precharge scheme are successfully applied to realize the excellent performance combination of high-speed operation and low-power dissipation. The CMOS peripheral circuitry is capable of the new operating functions, fast page mode, or static column mode with metal mask options. The typical RAS access time is 56 ns, the active current is 30 mA at a 190-ns cycle time, and the standby current is 0.2 mA.