A 256K CMOS SRAM with variable impedance data-line loads

A 256K (32K/spl times/8) CMOS SRAM utilizing variable impedance loads and a pulsed word-line (PWL) technique is described. In the WRITE cycle, the variable impedance loads of the data lines enter a high impedance state and reduce the operating power. During the READ cycle, the PWL technique is used to achieve high-speed operation and low power dissipation. The internal clocks generated by the address transition detectors activate word-line and sense amplifiers for READ operation and disable them after the data are sent to D/SUB out/ buffers. This PWL technique eliminates the precharge time of 20 ns, which corresponds to 30% of the access time. The RAM offers 45-ns address access time and 40-mW operating power in the WRITE cycle of 1 MHz.