Title :
Experimental 0.1 mu m p-channel MOSFET with p/sup +/-polysilicon gate on 35 AA gate oxide
Author :
Taur, Yuan ; Cohen, S. ; Wind, S. ; Lii, T. ; Hsu, C. ; Quinlan, D. ; Chang, C.A. ; Buchanan, Doug ; Agnello, Paul ; Mii, Yuh-Jier ; Reeves, C. ; Acovic, Alexandre ; Kesan, Vijay
Author_Institution :
IBM Thomas J. Watson Center, Yorktown Heights, NY, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
Very-high-transconductance 0.1 mu m surface-channel pMOSFET devices are fabricated with p/sup +/-poly gate on 35 AA-thick gate oxide. A 600 AA-deep p/sup +/ source-drain extension is used with self-aligned TiSi/sub 2/ to achieve low series resistance. The saturation transconductances, 400 mS/mm at 300 K and 500 mS/mm at 77 K, are the highest reported to date for pMOSFET devices.<>
Keywords :
insulated gate field effect transistors; semiconductor technology; 0.1 micron; 300 K; 35 AA; 400 mS/mm; 500 mS/mm; Si-SiO/sub 2/; gate oxide; low series resistance; p-channel MOSFET; p/sup +/ source-drain extension; p/sup +/-polysilicon gate; saturation transconductances; selfaligned TiSi/sub 2/; surface-channel pMOSFET devices; Boron; Electron devices; Etching; Fabrication; Lithography; MOSFET circuits; Resists; Surface resistance; Threshold voltage; Tunneling;
Journal_Title :
Electron Device Letters, IEEE
