Title :
A fast 8Kx8 CMOS SRAM with internal power down design techniques
Author :
Sood, Lal C. ; Golab, James S. ; Salter, John ; Leiss, John E. ; Barnes, John J.
Abstract :
A 35-ns 8K/spl times/8 CMOS SRAM with address-transition detection design techniques and a novel architecture is described. This design uses a 1.5-/spl mu/m HCMOS twin-well process with polycide gates. A technique for generating internal timing which is impervious to address skew and glitches has been developed. At long cycle times the circuit automatically powers down to a 8-mA active current level with the part selected.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Circuit synthesis; Clocks; Decoding; Driver circuits; Microprocessors; Pulse amplifiers; Pulse circuits; Pulse generation; Random access memory; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1985.1052419
