Threshold voltage based CMOS voltage reference

The paper describes a CMOS voltage reference design that uses the temperature dependence of NMOS and PMOS threshold voltages to form a temperature-insensitive reference. No diodes or parasitic bipolar transistors are used. The circuit architecture accommodates a wide range of output voltages. A test chip is fabricated using a 0.5 μm CMOS process. The prototype achieves a temperature coefficient of 32 ppm/°C for a temperature range of -10°C to 80°C and a supply voltage sensitivity of 10 mV/V.