• DocumentCode
    899411
  • Title

    An 8-MHz CMOS subranging 8-bit A/D converter

  • Author

    Dingwall, Andrew G F ; Zazzu, Victor

  • Volume
    20
  • Issue
    6
  • fYear
    1985
  • Firstpage
    1138
  • Lastpage
    1143
  • Abstract
    A 8-bit subranging converter (ADC) has been realized in a 3-/spl mu/m silicon gate, double-polysilicon capacitor CMOS process. The ADC uses 31 comparators and is capable of conversion rates to 8 MHz at V/SUB DD/=5 V. Die size is 3.2/spl times/2.2 mm/SUP 2/.
  • Keywords
    Analogue-digital conversion; CMOS integrated circuits; analogue-digital conversion; CMOS logic circuits; CMOS process; Capacitors; Clocks; Costs; Digital signal processing; Linearity; Power dissipation; Silicon; Throughput;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1985.1052451
  • Filename
    1052451
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=899411