Title :
A flexible gate array architecture for high-speed and high-density applications
Author :
Gallia, James D. ; Landers, Robert J. ; Shaw, Ching-hao ; Blake, Terence G W ; Banzhaf, Wally
Author_Institution :
Semicond. Process & Device Center, Texas Instrum. Inc., Dallas, TX, USA
fDate :
3/1/1996 12:00:00 AM
Abstract :
A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm2 routed density in a 0.5 μm TLM CMOS gate array. Compared to previous 5 V 0.7 μm gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM´s feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; logic arrays; 0.5 micron; 170 ps; 3.3 V; 3.9 ns; TGC3000; TLM CMOS gate array; flexible gate array architecture; high-density applications; high-speed applications; metal-programmable two-port SRAM; scaleable gate array; static RAM; BiCMOS integrated circuits; CMOS logic circuits; CMOS technology; Delay; Flip-flops; Logic arrays; Logic design; Logic gates; Programmable logic arrays; Wiring;
Journal_Title :
Solid-State Circuits, IEEE Journal of
