Title :
Timing verification of dynamic circuits
Author :
Venkat, Kumar ; Chen, Liang ; Lin, Ichiang ; Mistry, Piyush ; Madhani, Pravin
Author_Institution :
Suryn Technol. Inc., San Jose, CA, USA
fDate :
3/1/1996 12:00:00 AM
Abstract :
A complete set of rules is presented for timing verification of domino-style dynamic circuits. These rules include identification of dynamic nodes, generation of accurate timing constraints based on the operating environment of the gate and verification as an enhanced part of a complete timing verification process. This methodology has been implemented in a new static timing verifier and used to verify microprocessor circuits
Keywords :
combinational circuits; computer testing; integrated circuit testing; logic testing; microprocessor chips; timing circuits; domino-style dynamic circuits; dynamic nodes; microprocessor circuits; static timing verifier; timing constraints; timing verification; Clocks; Coupling circuits; Energy consumption; Error correction; Latches; Logic; Microprocessors; Space vector pulse width modulation; Timing; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
