Plate-noise analysis of an on-chip generated half-VDD biased-plate PMOS cell in CMOS DRAMs

An on-chip generated half-VDD bias for the memory-cell plate is used in CMOS DRAMS to reduce the electric field in the storage insulator such that higher capacitor reliability can be achieved or a thinner insulator can be used to give larger capacitance. A detailed plate-noise analysis shows that the on-chip generated plate bias is useful if a stable substrate bias is provided for the memory array and if the half-VDD sensing scheme proposed by N.C.C. Lu and H. Chao (1984) is used. The design of a half-VDD biased-plate PMOS cell in an n-well CMOS DRAM is also described.