Sorter Based Permutation Units for Media-Enhanced Microprocessors

Author

Dimitrakopoulos, Giorgos ; Mavrokefalidis, Christos ; Galanopoulos, Kostas ; Nikolos, Dimitris

Author_Institution

Patras Univ., Patras

Volume

15

Issue

6

fYear

2007

fDate

6/1/2007 12:00:00 AM

Firstpage

711

Lastpage

715

Abstract

Single or multibit subword permutations are useful in many multimedia and cryptographic applications. Several specialized instructions have been proposed to handle the required data rearrangements. In this paper, we examine the hardware implementation of the powerful permutation instruction group (GRP). The design of the proposed permutation unit is based on the functionality of sorting networks. Two variants of the sorter-based GRP unit are introduced and analyzed and their energy-delay behavior is investigated using static CMOS implementations in a 130-nm CMOS technology.

Keywords

CMOS integrated circuits; application specific integrated circuits; cryptography; microprocessor chips; multimedia systems; sorting; CMOS technology; cryptography; data rearrangements; energy-delay behavior; media-enhanced microprocessors; multimedia applications; permutation instruction group; sorter based permutation units; static CMOS implementations; subword permutations; CMOS technology; Circuits; Cryptography; Hardware; Microprocessors; Multimedia computing; Parallel processing; Software algorithms; Software performance; Sorting; Cryptography; data-rearrangement instructions; multimedia processors; permutation units; sorting networks;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2007.898750

Filename

4231881