DocumentCode
899719
Title
Registers for Phase Difference Based Logic
Author
Shang, D. ; Yakovlev, A. ; Koelmans, A. ; Sokolov, D. ; Bystrov, A.
Author_Institution
Newcastle Univ., Newcastle
Volume
15
Issue
6
fYear
2007
fDate
6/1/2007 12:00:00 AM
Firstpage
720
Lastpage
724
Abstract
A logic design style known as phase difference-based logic (PDBL) has several benefits with respect to security and testing. An existing design method for PDBL circuits has so far been lacking an important component, a register. In this paper, we present the design of a speed independent PDBL register and a timed PDBL register, which can be used in asynchronous or synchronous circuits. Comparisons are presented in terms of speed, size, and power consumption.
Keywords
asynchronous circuits; flip-flops; logic design; shift registers; PDBL circuits design; asynchronous circuits; logic design style; phase difference-based logic circuits; power consumption; speed independent PDBL register; synchronous circuits; timed PDBL register; Circuit testing; Encoding; Logic design; Logic gates; Logic testing; Protocols; Registers; Security; Switches; Switching circuits;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2007.898772
Filename
4231889
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