A numerically stable pipeline net VLSI architecture for the isomorphic Hopfield model

Author

Chang, Po-Rong ; Yeh, Bao-Fuh

Author_Institution

Dept. of Commun. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

Volume

41

Issue

5

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

2013

Lastpage

2017

Abstract

An isomorphic model is introduced to reduce the complexity of the Hopfield model´s digital implementations. To ensure numerical solution with stability and a prescribed accuracy, a mixed-type integration algorithm based on combining a single-step Runge-Kutta method and a multistep predictor-corrector method is applied to the digital simulation of the isomorphic model. A reconfigurable pipeline net VLSI architecture is proposed to implement the mixed-type integration algorithm. The architecture is composed of four processors, a programmable 12×30 routing network, and a 6×n shifter array, which are assigned to deal with the main operations of the integration algorithm, data routing, and synchronization, respectively

Keywords

Hopfield neural nets; Runge-Kutta methods; VLSI; integration; neural chips; pipeline processing; predictor-corrector methods; systolic arrays; digital simulation; isomorphic Hopfield model; mixed-type integration algorithm; multistep predictor-corrector method; neural networks; numerically stable pipeline net VLSI architecture; processors; programmable routing network; shifter array; single-step Runge-Kutta method; systolic array; Artificial neural networks; Computer architecture; Computer networks; Concurrent computing; Neural networks; Neurons; Numerical models; Pipeline processing; Polynomials; Very large scale integration;

fLanguage

English

Journal_Title

Signal Processing, IEEE Transactions on

Publisher

ieee

ISSN

1053-587X

Type

jour

DOI

10.1109/78.215328

Filename

215328