32K read-only-memory chip design in Josephson technology: a feasibility study

The results of a feasibility study of a 32K read-only-memory (ROM) chip design in Josephson technology are presented. Operating principles and design criteria used for the Josephson ROM (J-ROM) chip components, such as the memory cell, the sense bus, multiplexers, and the complement address generation circuits, are described. The various design constraints on the chip components imposed by the requirement for high speed, high density, high design-limited yield, and wide operating margins, in conjunction with system aspects, are also shown and discussed in detail. The impact of different ROM chip architectures on the memory performance and chip size is then estimated based on preliminary computer simulations.