Fast Parallel-Prefix Architectures for Modulo 2n-1 Addition with a Single Representation of Zero

Novel modulo 2ⁿ-1 addition algorithms for residue number system (RNS) applications are presented. The proposed algorithms depart from the traditional approach of modulo 2ⁿ-1 addition by setting the input carry in the first stage of the addition to one, which only ever produces one representation of zero. The resulting architectures not only offer significant speedup in a modulo 2ⁿ-1 addition, but they can also offer a reduction in area and thus provide improvements in the cost functions area times delay² and energy times delay. The superiority of these architectures is validated through back-annotated VLSI designs using 130 nm CMOS technology.