Sample-set differential logic (SSDL) for complex high-speed VLSI

An improved CMOS logic circuitusing a differential cascode tree with sample and set phases of operation is presented. The sample-set differential logic (SSDL) circuit allows the use of several transistors in series in the cascode tree without significant speed degradation. Also, the signals arriving at the input require only a short valid time, which allows long interconnect delays. This improved logic circuits is compared with two other common CMOS logic circuits in a simulated design example.