Title :
A High-Performance N-MOS Adder Designed for Optimized Cryogenic Operation
Author :
Glories, P. ; Boudou, A. ; Doyle, Bruce ; Leclaire, P. ; Chantraine, P.
fDate :
6/1/1986 12:00:00 AM
Abstract :
Low-temperature MOS devices (77 K) present significant gain in speed and density for a low technological cost. An N-MOS process has been adapted for use at liquid-nitrogen temperature using argon-implanted polysilicon resistors of very small dimensions as loads, instead of depleted devices. A ripple-carry 3-bit adder has been designed with 3- and 2.4-μm roles to estimate the speed-power possibilities of the technology. It uses complex gates with quasi-static memorizing, and yields a maximum measured frequency of 405 MHz for a 28-mW power consumption, with 2.4-μm design rules. This can be compared with results from the same circuit realized with other technologies (GaAs, 1-μm N-MOS,˙˙˙).
Keywords :
Adders; Cryogenic electronics; MOS integrated circuits; Adders; Costs; Cryogenics; Design optimization; Energy consumption; Frequency measurement; MOS devices; Power measurement; Resistors; Temperature;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052542
