DocumentCode
900474
Title
A CMOS Four-Quadrant Analog Multiplier
Author
Bult, Klaas ; Wallinga, Hans
Volume
21
Issue
3
fYear
1986
fDate
6/1/1986 12:00:00 AM
Firstpage
430
Lastpage
435
Abstract
A new circuit configuration for an MOS four-quadrant analog multiplier circuit is presented. It is based on the square-law characteristics of the MOS transistor. Two versions have been realized. The first has a linearity better than 0.14 percent for an output current swing of 36 percent of the supply current and a bandwidth from dc to 1 MHz. The second version has floating inputs, a linearity of 0.4 percent at an output current swing of 40 percent of the supply current and a bandwidth from dc to above 4.5 MHz.
Keywords
CMOS analog integrated circuits; Multiplying circuits; Adaptive filters; Bandwidth; CMOS technology; Circuits; Converters; Current supplies; Geometry; Linearity; MOSFETs; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052546
Filename
1052546
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