Title :
An ichnographic two-dimensional analysis of the MOS LSI mask layout pattern
fDate :
6/1/1986 12:00:00 AM
Abstract :
This simulation technique is particularly suitable for analyzing the electric property of a MOSFET or a part of an MOS LSI, taking account of the source-drain average resistivity of the diffused area and the layout pattern effect. The algorithm is presented and calculated examples are given. The simulated result shows satisfactory agreement with the experimental data. The scaling property and the layout pattern effect of the MOSFET were also investigated with the use of this simulation technique.
Keywords :
Circuit layout CAD; circuit layout CAD; Circuit simulation; Conductivity; Dielectric substrates; Geometry; Large scale integration; MOS devices; MOSFET circuits; Numerical analysis; Pattern analysis; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052551
