DocumentCode
900523
Title
An ichnographic two-dimensional analysis of the MOS LSI mask layout pattern
Author
Natori, Kenji
Volume
21
Issue
3
fYear
1986
fDate
6/1/1986 12:00:00 AM
Firstpage
457
Lastpage
463
Abstract
This simulation technique is particularly suitable for analyzing the electric property of a MOSFET or a part of an MOS LSI, taking account of the source-drain average resistivity of the diffused area and the layout pattern effect. The algorithm is presented and calculated examples are given. The simulated result shows satisfactory agreement with the experimental data. The scaling property and the layout pattern effect of the MOSFET were also investigated with the use of this simulation technique.
Keywords
Circuit layout CAD; circuit layout CAD; Circuit simulation; Conductivity; Dielectric substrates; Geometry; Large scale integration; MOS devices; MOSFET circuits; Numerical analysis; Pattern analysis; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052551
Filename
1052551
Link To Document