Title :
A full adder using junction charge-coupled logic
Author :
Van Der Klauw, Cornelis L M
fDate :
8/1/1986 12:00:00 AM
Abstract :
A full adder that is based on three-dimensional charge transport in junction charge-coupled devices (JCCDs) is presented. The basic current uses little chip area and is operated by a three-phase clock. No DC voltages are required for logic operation. The SUM and CARRY signals are calculated within one clock cycle. The concept of this full adder is suited to application in systolic arrays.
Keywords :
Adders; Charge-coupled device circuits; adders; charge-coupled device circuits; Adders; Charge coupled devices; Circuits; Clocks; Communication switching; Computational modeling; Electrons; Logic; Signal processing algorithms; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1986.1052576
