An experimental 4-Mbit CMOS DRAM

Author

Furuyama, Tohru ; Ohsawa, Takashi ; Watanabe, Yohji ; Ishiuchi, Hidemi ; Watanabe, Toshiharu ; Tanaka, Takeshi ; Natori, Kenji ; Ozawa, Osamu

Volume

21

Issue

5

fYear

1986

fDate

10/1/1986 12:00:00 AM

Firstpage

605

Lastpage

611

Abstract

A 4-Mb dynamic RAM has been designed and fabricated using 1.0-μm twin-tub CMOS technology. The memory array consists of trenched n-channel depletion-type capacitor cells in a p-well. Very high α-particle immunity was achieved with this structure. One cell measures 3.0×5.8 μm/SUP 2/ yielding a chip size of 7.84×17.48 mm/SUP 2/. An on-chip voltage converter circuit was implemented as a mask option to investigate a possible solution to the MOSFET reliability problem caused by hot carriers. An 8-bit parallel test mode was introduced to reduce the RAM test time. Metal mask options provide static-column-mode and fast-age-mode operation. The chip is usable as ×1 or ×4 organizations with a bonding option. Using an external 5-V power supply, the row-address-strobe access time is 80 ns at room temperature. The typical active current is 60 mA at a 220-ns cycle time with a standby current of 0.5 mA.

Keywords

CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; CMOS technology; Capacitors; Circuit testing; DRAM chips; Hot carriers; MOSFET circuits; Random access memory; Semiconductor device measurement; Size measurement; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1986.1052584

Filename

1052584