DocumentCode
900891
Title
A 4-Mbit DRAM with half-internal-voltage bit-line precharge
Author
Takada, Masahide ; Takeshima, Toshio ; Sakamoto, Mitsuru ; Shimizu, Toshiyuki ; Abiko, Hitoshi ; Katoh, Takuya ; Kikuchi, Masanori ; Takahashi, Sakari ; Sato, Yoshinori ; Inoue, Yasukazu
Volume
21
Issue
5
fYear
1986
fDate
10/1/1986 12:00:00 AM
Firstpage
612
Lastpage
617
Abstract
A single 5-V supply 4-Mb dynamic random access memory (DRAM) was developed by using a buried-storage-electrode memory cell, a half-internal-voltage bit-line precharge method combined with a constant voltage converter, and a high signal-to-noise ratio sensing scheme. The chip was designed in a double-polycide, single-Al, epitaxial substrate NMOS technology with a 0.8-μm minimum design rule. As a result, a 4M word×1-bit DRAM with 95-ns typical access time and 99.2-mm/SUP 2/ chip area was attained by 10.58-μm/SUP 2/ storage cells.
Keywords
Field effect integrated circuits; Integrated memory circuits; Random-access storage; field effect integrated circuits; integrated memory circuits; random-access storage; Capacitance; Capacitors; Circuits; Degradation; Electrodes; MOS devices; Random access memory; Signal to noise ratio; Substrates; Voltage;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052585
Filename
1052585
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