DocumentCode
900983
Title
A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM
Author
Homma, Noriyuki ; Yamaguchi, Kunihiko ; Nanbu, Hiroaki ; Kanetani, Kazuo ; Nishioka, Yasushiro ; Uchida, Akihisa ; Ogiue, Katsumi
Volume
21
Issue
5
fYear
1986
fDate
10/1/1986 12:00:00 AM
Firstpage
675
Lastpage
680
Abstract
A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 μm/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-μm U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.
Keywords
Bipolar integrated circuits; Emitter-coupled logic; Integrated memory circuits; Random-access storage; bipolar integrated circuits; emitter-coupled logic; integrated memory circuits; random-access storage; Capacitors; Decoding; Driver circuits; Isolation technology; Latches; Logic; Power dissipation; Schottky barriers; Schottky diodes; System-on-a-chip;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1986.1052594
Filename
1052594
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