DocumentCode :
901138
Title :
A 19-ns 250-mW CMOS erasable programmable logic device
Author :
Pathak, Jagdish ; Kurkowski, Hal ; Pugh, Robert ; Shrivastava, Ritu ; Jenne, Frederick B.
Volume :
21
Issue :
5
fYear :
1986
fDate :
10/1/1986 12:00:00 AM
Firstpage :
775
Lastpage :
784
Abstract :
A 19-ns 250-mW erasable programmable logic device using 1.2-μm n-well CMOS EPROM technology is described. CMOS EPROM technology and new circuit techniques give smaller die and lower power than SSI/MSI logic components without compromising speed. A novel cell current tracking, temperature-compensated sense amplifier is used to enhance performance and reduce power. The versatile macrocell makes the logic implementation simpler, and the EPROM technology gives improved programmability and reliability.
Keywords :
CMOS integrated circuits; Cellular arrays; Integrated logic circuits; Logic design; cellular arrays; integrated logic circuits; logic design; CMOS technology; Dielectric substrates; EPROM; Fuses; Logic devices; Programmable logic arrays; Programmable logic devices; Space technology; Testing; Threshold voltage;
fLanguage :
English
Journal_Title :
Solid-State Circuits, IEEE Journal of
Publisher :
ieee
ISSN :
0018-9200
Type :
jour
DOI :
10.1109/JSSC.1986.1052606
Filename :
1052606
Link To Document :
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