• DocumentCode
    901429
  • Title

    An 8-bit high-speed CMOS A/D converter

  • Author

    Kumamoto, Toshio ; Nakaya, Masao ; Honda, Hiroki ; Asai, Sotoju ; Akasaka, Yoichi ; Horiba, Yasutaka

  • Volume
    21
  • Issue
    6
  • fYear
    1986
  • fDate
    12/1/1986 12:00:00 AM
  • Firstpage
    976
  • Lastpage
    982
  • Abstract
    An 8-bit high-speed A/D converter has been developed in a 1.5-μm bulk CMOS double-polysilicon process technology. The design, process technology, and performance of the converter are described. In order to achieve high speed and low power, a fine-pattern process technology and a novel capacitor structure have been introduced and the transistor sizes of a chopper-type comparator have been optimized. High speed (30 MS/s) and low power consumption (60 mW) have been obtained. Computerized evaluations such as the histogram test and the fast Fourier transform test have been used to measure dynamic performance. The linearity error in dynamic operation is less than ±1 LSB. Signal-to-peak-noise ratio is 40 dB at a sampling rate of 14.32 MS/s and an input frequency of 1.42 MHz.
  • Keywords
    Analogue-digital conversion; CMOS integrated circuits; analogue-digital conversion; CMOS process; CMOS technology; Capacitors; Computer errors; Energy consumption; Fast Fourier transforms; Histograms; Linearity; Process design; Testing;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1986.1052638
  • Filename
    1052638