An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold

A monolithic, 8-bit, 250 megasample per second analog-to-digital converter (ADC) fabricated in an oxide-isolated bipolar process is described. The use of a flash ADC architecture at high speeds without a sample and hold leads to a number of error sources. The design of the converter is optimized to minimize the effects of these error sources. Experimental results are presented and compared with theory.