Design and implementation of quaternary NMOS integrated circuits for pipelined image processing

Author

Kameyama, Michitaka ; Hanyu, Takahiro ; Higuchi, Tatsuo

Volume

22

Issue

1

fYear

1987

fDate

2/1/1987 12:00:00 AM

Firstpage

20

Lastpage

27

Abstract

A pattern-matching procedure for performing four-valued image processing based on cellular logic operation is proposed, allowing two different templates to be processed simultaneously in a pipelined manner. Based on these double pattern-matching cells, a compact NMOS image-processing chip has been implemented. It is demonstrated that the compactness comes from reduced interconnections in the double pattern-matching cells using a quaternary multiplexer or T gates, realized with pass transistors and multiple ion implants.

Keywords

Computerised picture processing; Field effect integrated circuits; Integrated circuit technology; Integrated logic circuits; Many-valued logics; Pipeline processing; computerised picture processing; field effect integrated circuits; integrated circuit technology; integrated logic circuits; many-valued logics; pipeline processing; Color; Hardware; Image processing; Implants; Integrated circuit interconnections; Logic arrays; MOS devices; Multiplexing; Pattern matching; Pixel;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.1987.1052666

Filename

1052666