• DocumentCode
    901774
  • Title

    Novel recursive algorithm and highly compact semisystolic architecture for high throughput computation of 2-D DHT

  • Author

    Meher, Pramod Kumar ; Panda, Ganapati

  • Author_Institution
    Regional Eng. Coll., Rourkela, India
  • Volume
    29
  • Issue
    10
  • fYear
    1993
  • fDate
    5/13/1993 12:00:00 AM
  • Firstpage
    883
  • Lastpage
    885
  • Abstract
    A recursive algorithm and a fully pipelined semisystolic CORDIC architecture for computing the 2-D discrete Hartley transform are proposed. The proposed architecture has nearly eight times the throughput rate and requires nearly (1/8)th the chip area compared with the existing CORDIC architecture.
  • Keywords
    digital arithmetic; digital signal processing chips; parallel algorithms; pipeline processing; systolic arrays; transforms; 2D DHT; CORDIC architecture; DSP; compact semisystolic architecture; discrete Hartley transform; fully pipelined architecture; high throughput computation; recursive algorithm;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:19930590
  • Filename
    216289
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=901774