Title :
The analysis and design of CMOS multidrain logic and stacked multidrain logic
Author :
Wu, Chung-Yu ; Wang, Jinn-Shyan ; Tsai, Ming-Kai
fDate :
2/1/1987 12:00:00 AM
Abstract :
A CMOS logic circuit called the CMOS multidrain logic (MDL) is proposed, analyzed, and experimentally observed. The basic circuit structure, which is derived from integrated injection logic, consists of an enhancement-mode MOSFET as a current injector and a multidrain MOSFET with drain terminals as output nodes and the gate terminal as input node. As compared with the multidrain NMOS logic, the difference is that an enhancement MOS instead of a depletion NMOS is used as a current injector.
Keywords :
CMOS integrated circuits; Integrated circuit technology; Integrated logic circuits; VLSI; integrated circuit technology; integrated logic circuits; CMOS digital integrated circuits; CMOS logic circuits; CMOS memory circuits; CMOS technology; Degradation; Logic circuits; Logic design; Logic gates; MOS devices; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052670
