Title :
A decoder with OR gates for a Josephson high-density memory circuit
Author :
Igarashi, Takeshi ; Suzuki, Hideo ; Hasuo, Shinya ; Yamaoka, Toyoshi
fDate :
2/1/1987 12:00:00 AM
Abstract :
A decoder made of OR gates was designed for a Josephson high-density memory circuit. The advantages of this decoder are its large operating margin and high-speed operation compared with conventional decoders made of AND gates. The decoder was designed for a 16-Kbit random access memory (RAM), and was successfully operated with a delay time of 2 ns.
Keywords :
Integrated logic circuits; Integrated memory circuits; Random-access storage; Superconducting junction devices; Superconducting logic circuits; Superconducting memory circuits; integrated logic circuits; integrated memory circuits; random-access storage; superconducting junction devices; superconducting logic circuits; superconducting memory circuits; Circuit simulation; Decoding; Delay effects; Energy consumption; Flip-flops; Helium; Random access memory; Read-write memory; Switches; Switching circuits;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052675
