• DocumentCode
    902150
  • Title

    PLA folding by simulated annealing

  • Author

    Wong, D.F. ; Leong, H.W. ; Laung, C.L.

  • Volume
    22
  • Issue
    2
  • fYear
    1987
  • fDate
    4/1/1987 12:00:00 AM
  • Firstpage
    208
  • Lastpage
    215
  • Abstract
    A simulated-annealing programmable-logic array (PLA) folding algorithm is presented for simple as well as multiple-column folding. Experimental results indicate that the algorithm performs very well. In many test problems, the results are superior to those produced by the well-known heuristic algorithm of G. De Micheli and A. Sangiovanni-Vincentelli (1983). It is also shown that the algorithm can be extended to handle constrained folding.
  • Keywords
    Cellular arrays; Integrated logic circuits; Logic design; cellular arrays; integrated logic circuits; logic design; Circuit simulation; Computational modeling; Continuous wavelet transforms; Heuristic algorithms; Input variables; Logic arrays; Process design; Programmable logic arrays; Simulated annealing; Testing;
  • fLanguage
    English
  • Journal_Title
    Solid-State Circuits, IEEE Journal of
  • Publisher
    ieee
  • ISSN
    0018-9200
  • Type

    jour

  • DOI
    10.1109/JSSC.1987.1052704
  • Filename
    1052704
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=902150