Title :
A 256-channel C/SUP 2/MOS LSI time-switch using shift-register pipeline multiplexer
Author :
Hatano, Hiroshi ; Doi, Katsuyuki ; Iwamura, Jun
fDate :
4/1/1987 12:00:00 AM
Abstract :
SOS technology has been used to retain the pipeline processing speed advantage by controlling the capacitance of on-chip lines that must be long to provide 256-channel operation. Clocked CMOS (C/SUP 2/MOS) circuits have been used to avoid clock-skew problems. A 1.5-μm C/SUP 2/MOS/SOS technology has made it possible to integrate 900 transistors into a 4.0×2.4-mm/SUP 2/ area, and to realize a 256-channel time-switch LSI, with a 15-ns typical output delay time and a 300-mW power dissipation during 25-MHz operation.
Keywords :
CMOS integrated circuits; Digital integrated circuits; Integrated logic circuits; Large scale integration; Pipeline processing; Shift registers; Switching circuits; digital integrated circuits; integrated logic circuits; large scale integration; pipeline processing; shift registers; switching circuits; CMOS technology; Capacitance; Circuits; Clocks; Delay effects; Large scale integration; MOSFETs; Multiplexing; Pipeline processing; Power dissipation;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052709
