Title :
CDF level 2 trigger upgrade
Author :
Anikeev, K. ; Bogdan, M. ; Demaat, R. ; Fedorko, W. ; Frisch, H. ; Hahn, K. ; Hakala, M. ; Keener, P. ; Kim, Y. ; Kroll, J. ; Kwang, S. ; Lewis, J. ; Lin, C. ; Liu, T. ; Marjamaa, F. ; Mansikkala, T. ; Neu, C. ; Pitkanen, S. ; Reisert, B. ; Rusu, V. ; San
Author_Institution :
Fermi Nat. Accel. Lab., Batavia, IL, USA
fDate :
4/1/2006 12:00:00 AM
Abstract :
We describe the new CDF Level 2 Trigger, which was commissioned during Spring 2005. The upgrade was necessitated by several factors that included increased bandwidth requirements, in view of the growing instantaneous luminosity of the Tevatron, and the need for a more robust system, since the older system was reaching the limits of maintainability. The challenges in designing the new system were interfacing with many different upstream detector subsystems, processing larger volumes of data at higher speed, and minimizing the impact on running the CDF experiment during the system commissioning phase. To meet these challenges, the new system was designed around a general purpose motherboard, the PULSAR, which is instrumented with powerful FPGAs and modern SRAMs, and which uses mezzanine cards to interface with upstream detector components and an industry standard data link (S-LINK) within the system.
Keywords :
SRAM chips; field programmable gate arrays; nuclear electronics; particle detectors; CDF level 2 trigger upgrade; FPGA; PULSAR; S-LINK; SRAM; Tevatron; mezzanine cards; upstream detector subsystems; Bandwidth; Computer buffers; Detectors; Field programmable gate arrays; Hardware; Instruments; Phase detection; Physics; Robustness; Springs; FPGA based hardware; real-time systems; trigger;
Journal_Title :
Nuclear Science, IEEE Transactions on
DOI :
10.1109/TNS.2006.871782
