Design of PLL-based clock generation circuits

The design of clock generation circuitry being used as a part of a high-performance microprocessor chip set is described. A self-calibrating tapped delay line is used to generate four nonoverlapping clock phases of a system clock. A charge-pump phase-locked loop (PLL) calibrates the delay per stage of the delay line. Using this technique, it is possible to obtain an accurate phase relationship between the off-chip reference clock and the internal clock signals. Experimental results show that required timing relations can be obtained with less than 2-ns clock skew for frequencies from 1 to 18 MHz.