Calculation of Cosmic-Ray Induced Soft Upsets and Scaling in VLSI Devices

Progression of VLSI circuitry to smaller feature sizes raises questions about an increased severity of the cosmic ray upset problem. In this paper we present a simple method of calculating cosmic ray upset rates. We compare the results of this method to results of an exact calculation and apply both methods to the prediction of upset rates as device feature sizes are scaled to submicron dimensions. The exact calculations are presented for several environmental predictions. We then discuss upset critical charge as a function of feature size. We consider upset rates versus scale parameter as a function of device size and critical charge. We conclude that upset rates do not increase catastrophically as devices scale down, but that the problem will be serious for all technologies. We also conclude that devices with small feature sizes will be susceptible to upsets by proton induced reactions, so that they will have serious problems in the proton radiation belt.