Title :
A 16-level/cell dynamic memory
Author :
Aoki, Masakazu ; Nakagome, Yoshinobu ; Horiguchi, Masahi ; Ikenaga, Shin Ichi ; Shimohigashi, Katsuhiro
fDate :
4/1/1987 12:00:00 AM
Abstract :
A multilevel storage dynamic memory using a standard DRAM memory cell array is presented. A staircase word pulse and a charge-transfer preamplifier are used for converting binary data to multilevel storage voltages and vice versa. The 16-level (4-bit)/cell READ/WRITE operation has been confirmed at storage levels as low as 80-100 mV. The storage-level voltage accuracy is limited basically by subthreshold leakage current.
Keywords :
Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Capacitance; Large scale integration; MOS devices; Multilevel systems; Preamplifiers; Random access memory; Solid state circuits; Subthreshold current; Threshold voltage; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052717
