DocumentCode :
902506
Title :
Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff
Author :
Hentschke, Renato ; Narasimhan, J. ; Johann, Marcelo ; Reis, Ricardo
Author_Institution :
Inst. de Inf., Univ. Fed. do Rio Grande do Sul (UFRGS), Porto Alegre, Brazil
Volume :
17
Issue :
8
fYear :
2009
Firstpage :
1073
Lastpage :
1086
Abstract :
In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a maze router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal topologies in average. By introducing a sharing factor and a path-length factor we show how to trade-off wire length for delay. Experimental results show that our algorithm generates topologies with better delay compared to state of the art heuristics for Steiner trees, such as AHHK (from 26% to 40%) and P-Trees (from 1% to 30% and from 6% to 21% in the presence of blockages) while keeping the properties of a routing algorithm. An important motivation for this work lies in the fact that it can be used for estimation in the early stages as well as for actual routing, thereby improving the convergence and timing closure of the design significantly. We also provide some valuable theoretical background and insights on delay optimization and on how it relates to our maze router implementation.
Keywords :
search problems; telecommunication network routing; trees (mathematics); maze routing Steiner trees; path search algorithms; path-length factor; rectilinear Steiner tree; sharing factor; wire length improvement; Delay; Steiner trees; maze search; routing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2009.2019798
Filename :
4957020
Link To Document :
بازگشت