DocumentCode
902549
Title
A 32-Kbit variable-length shift register for digital audio application
Author
Pelgrom, Marcel J M ; Termeer, Andhenk A H
Volume
22
Issue
3
fYear
1987
fDate
6/1/1987 12:00:00 AM
Firstpage
415
Lastpage
422
Abstract
On the chip described, dynamic shift registers are combined with high-density serial-parallel-serial charge-coupled-device (SPS CCD) memory blocks in order to obtain a switchable chain of delay blocks with delay values that are powers of two. The shift-register length can be adjusted from 17 to 32767 clock periods. The tradeoff between the delay implementations is presented. A detailed description of the SPS CCD are given. The chip has been realized in a 2.5-μm NMOS process with CCD option.
Keywords
Audio equipment; Charge-coupled device circuits; Computerised signal processing; Delay lines; Field effect integrated circuits; Integrated memory circuits; Shift registers; Signal processing equipment; audio equipment; charge-coupled device circuits; computerised signal processing; delay lines; field effect integrated circuits; integrated memory circuits; shift registers; signal processing equipment; Bonding; Charge coupled devices; Clocks; Delay; Digital signal processing; Flip-flops; Random access memory; Read-write memory; Shift registers; Switches;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052741
Filename
1052741
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