Abstract :
The design and operation of a CMO-bipolar SRAM cell, which incorporates cross-coupled CMOS and n-p-n access transistors, is discussed. A column circuitry to accompany this cell is proposed. Simulation results attributing column access time, standby power dissipation, and active power dissipation of 6-8 ns, 6.5 nW/bit, and 4 mW/b, respectively, for a cell area of ~450 μm/SUP 2/, suggest the suitability of this approach for applications requiring density, performance, and moderate power.
Keywords :
Bipolar integrated circuits; CMOS integrated circuits; Integrated memory circuits; Random-access storage; bipolar integrated circuits; integrated memory circuits; random-access storage; Inverters; Lifting equipment; Logic devices; Power dissipation; Random access memory; Read-write memory; Signal to noise ratio; Solid state circuit design; Solid state circuits; Timing;
