DocumentCode
903022
Title
On the analysis and design of CMOS-bipolar SRAMs
Author
De-Los Santos, H. ; Hoefflinger, Bernd
Volume
22
Issue
4
fYear
1987
fDate
8/1/1987 12:00:00 AM
Firstpage
616
Lastpage
619
Abstract
The design and operation of a CMO-bipolar SRAM cell, which incorporates cross-coupled CMOS and n-p-n access transistors, is discussed. A column circuitry to accompany this cell is proposed. Simulation results attributing column access time, standby power dissipation, and active power dissipation of 6-8 ns, 6.5 nW/bit, and 4 mW/b, respectively, for a cell area of ~450 μm/SUP 2/, suggest the suitability of this approach for applications requiring density, performance, and moderate power.
Keywords
Bipolar integrated circuits; CMOS integrated circuits; Integrated memory circuits; Random-access storage; bipolar integrated circuits; integrated memory circuits; random-access storage; Inverters; Lifting equipment; Logic devices; Power dissipation; Random access memory; Read-write memory; Signal to noise ratio; Solid state circuit design; Solid state circuits; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/JSSC.1987.1052781
Filename
1052781
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