Title :
Noise-generation analysis and noise-suppression design techniques in megabit DRAMs
Author :
Itoh, Y. ; Nakagawa, K. ; Sakui, K. ; Horiguchi, F. ; Ogura, M.
fDate :
8/1/1987 12:00:00 AM
Abstract :
A detailed noise-generation model of peak current and voltage-bouncing noise for DRAMs is presented. This model was found to be a very effective tool for predicting and analyzing quantitative bouncing noise level in noise-suppress circuit design, especially for high-performance high-density DRAMs. The resulting performance for the fabricated NMOS 1-Mb DRAM is 100-mA peak current, 6-mA/ns current transition rate, and 0.27-V output voltage-bouncing noise for a standard system board.
Keywords :
Electron device noise; Field effect integrated circuits; Integrated memory circuits; Interference suppression; Random-access storage; electron device noise; field effect integrated circuits; integrated memory circuits; interference suppression; random-access storage; BiCMOS integrated circuits; Circuit noise; Circuit synthesis; MOS devices; Noise level; Random access memory; Solid state circuit design; Solid state circuits; Very large scale integration; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052782
