DocumentCode :
903079
Title :
Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging
Author :
Oruklu, Erdal ; Saniie, Jafar
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Inst. of Technol., Chicago, IL, USA
Volume :
58
Issue :
8
fYear :
2009
Firstpage :
2856
Lastpage :
2866
Abstract :
Ultrasonic imaging algorithms, including detection and compression, are computationally complex and difficult to implement in hardware for real-time applications. In this paper, we present an ultrasonic reconfigurable subband decomposition processor (RSDP) that can employ wavelet filters for frequency diverse signal processing. This architecture enables parallel implementation of a lifting-based discrete wavelet transform. The configurability of the architecture applies to the selection of wavelet kernels and scales for subband decomposition, thresholding operation for compression, and the postprocessing detection algorithm. The underlying hardware design makes use of the fact that both compression and detection applications share the same algorithm fundamentals. A unified architecture has been designed that implements signal decomposition and reconstruction with forward and inverse discrete wavelet transforms. After the forward transform step, a windowing operation is applied to discriminate frequency bands for target detection. Using the same architecture, a thresholding operation is applied to wavelet coefficients for data compression. The flexibility and the modular design make this reconfigurable architecture an effective and practical solution for real-time ultrasonic imaging applications. The resulting architecture is adaptable, fast, and suitable for a system-on-a-chip implementation that requires minimal logic resources.
Keywords :
data compression; discrete wavelet transforms; field programmable gate arrays; reconfigurable architectures; signal detection; signal reconstruction; system-on-chip; ultrasonic imaging; computationally complex; data compression; data reconstruction; dynamically reconfigurable architecture design; field-programmable gate array; forward transforms; frequency diverse signal processing; inverse discrete wavelet transforms; lifting-based discrete wavelet transform; parallel implementation; postprocessing detection algorithm; reconfigurable subband decomposition processor; signal decomposition; system-on-a-chip implementation; target detection; thresholding operation; ultrasonic imaging; wavelet filter; wavelet kernel; windowing operation; Compression; detectors; field-programmable gate array (FPGA); reconfigurable architectures; wavelet transforms;
fLanguage :
English
Journal_Title :
Instrumentation and Measurement, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9456
Type :
jour
DOI :
10.1109/TIM.2009.2016370
Filename :
4957075
Link To Document :
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