Modeling and optimization of substrate resistance for RF-CMOS

Author

Chang, Richard T. ; Yang, Ming-Ta ; Ho, Patricia P C ; Wang, Yo-Jen ; Chia, Yu-Tai ; Liew, Boon-Khim ; Yue, C. Patrick ; Wong, S. Simon

Author_Institution

Stanford Univ., CA, USA

Volume

51

Issue

3

fYear

2004

fDate

3/1/2004 12:00:00 AM

Firstpage

421

Lastpage

426

Abstract

A predictive, physically based substrate resistance model for CMOS transistors operating at radio frequencies (RF) is described. This analytical model is scalable with transistor size and layout geometry. Measurement results confirm that the model accurately predicts the effect of substrate resistance on the transistor output impedance up to 20 GHz, including gate and drain bias dependencies. Minimization of the substrate resistance can be achieved by using substrate tap rings with small spacer distances and short finger widths.

Keywords

CMOS integrated circuits; contact resistance; radiofrequency integrated circuits; CMOS transistors; RF-CMOS; drain bias; finger widths; gate bias; high-frequency MOSFET; high-frequency measurements; radio frequencies; radio frequency device modeling; spacer distances; substrate resistance minimization; substrate tap rings; transistor layout geometry; transistor output impedance; transistor size; Circuit simulation; Electrical resistance measurement; Fingers; Impedance; MOSFETs; Predictive models; Radio frequency; Semiconductor device manufacture; Semiconductor device modeling; Substrates;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2003.822586

Filename

1268268