Impact of reducing STI-induced stress on layout dependence of MOSFET characteristics

Active-area layout dependence of MOSFET parametric characteristics and its reduction by reducing shallow trench isolation (STI)-induced mechanical stress were investigated. Threshold voltages (V_th) and saturation drain currents (I_ds) become sensitive to the active-area layout of MOSFET in scaled-down technology. This phenomenon is the effect of mechanical stress from STI edge, which reduces impurity diffusion in channel region and enhances carrier mobility. To reduce the STI-induced stress, we examined STI-wall-oxide nitridation and STI gap-fill-oxide densifying in pure N₂ ambient. These processes reduced the reoxidation of the STI wall oxide, therefore reduced the STI-induced stress. According to the new STI process, the active-area layout dependence of V_th and I_ds were reduced successfully.