The twin-port memory cell

A novel full-CMOS six-transistor memory cell that provides uncontested and overlapped two-port read accesses to one-cell, and concurrent READ/WRITE operations to separate cells, has been designed and functional test circuits is fabricated. This twin-port cell is based on the traditional cross-coupled inverter, but with a versatile access scheme. Balanced differential access transistors have given way to independent and complementary access transistors attached to a common readout node in the cell. Independent N-port and P-port word lines control the NMOS and PMOS access devices routing stored data to N and P bit lines, respectively. Each port has the potential of accessing a cell without interference from activities at other port even if addressing the same cell. This cell, with a complementary single bit line and access transistor per port structure, is only 11% larger than a similarly constructed conventional six-transistor single-port CMOS cell.