Title :
A 34-ns 1-Mbit CMOS SRAM using triple polysilicon
Author :
Wada, Tomohisa ; Hirose, Toshihiko ; Shinohara, Hirofumi ; Kawai, Yuji ; Yuzuriha, Kojiro ; Kohno, Yoshio ; Kayano, Shimpei
fDate :
10/1/1987 12:00:00 AM
Abstract :
A 128-kb word×8-b CMOS SRAM with an access time of 3 ns and a standby current of 2 μA is described. This RAM has been fabricated using triple-polysilicon and single-aluminum CMOS technology with 0.8-μm minimum design features. A high-resistive third polysilicon load has been developed to realize a low standby current. In order to obtain a faster access time, a 16-block architecture and a data-output presetting technique combined with address transition detection (ATD) are used. This RAM has a flash-clear function in which logical zeros are written into all memory cells in less than 1 μs.
Keywords :
CMOS integrated circuits; Integrated memory circuits; Random-access storage; integrated memory circuits; random-access storage; Batteries; CMOS technology; Circuits; Clocks; Decoding; Helium; Paper technology; Random access memory; Read-write memory; System testing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
DOI :
10.1109/JSSC.1987.1052806
